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rev.3.00, feb.02.2004, page 1 of 26 HN58V65AI series hn58v66ai series hn58v65a-sr series hn58v66a-sr series 64k eeprom (8-kword 8-bit) ready/ busy function, res function (hn58v66a) wide temperature range version rej03c0153-0300z (previous ade-203-759b(z) rev.2.0) rev. 3.00 feb.02.2004 description renesas technology?s hn58v65a series and hn5 8v66a series are electrically erasable and programmable eeprom?s organized as 8192-word 8-bit. they have realized high speed, low power consumption and high reliability by employing advanced mnos memory technology and cmos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features ? single supply: 2.7 to 5.5 v ? access time: ? 100 ns (max) at 2.7 v v cc < 4.5 v ? 70 ns (max) at 4.5 v v cc 5.5 v ? power dissipation: ? active: 20 mw/mhz (typ) ? standby: 110 w (max) ? on-chip latches: address, data, ce , oe , we ? automatic byte write: 10 ms (max) ? automatic page write (64 bytes): 10 ms (max) ? ready/ busy ? data polling and toggle bit ? data protection circuit on power on/off
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 2 of 26 features (cont) ? conforms to jedec byte-wide standard ? reliable cmos with mnos cell technology ? 10 5 erase/write cycles (in page mode) ? 10 years data retention ? software data protection ? write protection by res pin (only the hn58v66a series) ? operating temperature range: ? HN58V65AI/hn58v66ai series: ? 40 to +85 c ? hn58v65a-sr/hn58v66a-sr series: ? 20 to +85 c ? there are also lead free products. ordering information access time type no. 2.7 v v cc < 4.5 v 4.5 v v cc 5.5 v package hn58v65api-10 100 ns 70 ns 600 mil 28-pin plastic dip (dp-28) hn58v66api-10 100 ns 70 ns hn58v65afpi-10 100 ns 70 ns 400 mil 28-pin plastic sop (fp-28d) hn58v66afpi-10 100 ns 70 ns hn58v65ati-10 100 ns 70 ns 28-pin plastic tsop(tfp-28db) hn58v66ati-10 100 ns 70 ns hn58v65at-10sr 100 ns 70 ns hn58v66at-10sr 100 ns 70 ns hn58v65api-10e 100 ns 70 ns 600 mil 28-pin plastic dip (dp-28v) hn58v66api-10e 100 ns 70 ns lead free hn58v65afpi-10e 100 ns 70 ns 400 mil 28-pin plastic sop (fp-28dv) hn58v66afpi-10e 100 ns 70 ns lead free hn58v65ati-10e 100 ns 70 ns 28-pin plastic tsop(tfp-28dbv) hn58v66ati-10e 100 ns 70 ns lead free hn58v65at-10sre 100 ns 70 ns hn58v66at-10sre 100 ns 70 ns
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 3 of 26 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we nc a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 rdy/ busy a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss (top view) hn58v65api series hn58v65afpi series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we res a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 rdy/ busy a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss (top view) hn58v66api series hn58v66afpi series 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 rdy/ busy v cc we nc a8 a9 a11 oe (top view) hn58v65ati series hn58v65at-sr series 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 rdy/ busy v cc we res a8 a9 a11 oe (top view) hn58v66ati series hn58v66at-sr series 15 16 17 18 19 20 21 22 23 24 25 26 27 28
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 4 of 26 pin description pin name function a0 to a12 address input i/o0 to i/o7 da ta input/output oe output enable ce chip enable we write enable v cc power supply v ss ground rdy/ busy ready busy res * 1 reset nc no connection note: 1. this function is supported by only the hn58v66a series. block diagram note: 1. this function is supported by only the hn58v66a series. v v oe ce a5 a0 a6 a12 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch res rdy/ busy res * 1 * 1 to to to
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 5 of 26 operation table operation ce oe we res * 3 rdy/ busy i/o read v il v il v ih v h * 1 high-z dout standby v ih * 2 high-z high-z write v il v ih v il v h high-z to v ol din deselect v il v ih v ih v h high-z high-z write inhibit v ih ? ? v il ? ? data polling v il v il v ih v h v ol dout (i/o7) program reset v il high-z high-z notes: 1. refer to the recommended dc operating conditions. 2. : don?t care 3. this function supported by only the hn58v66a series. absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ?0.6 to +7.0 v input voltage relative to v ss vin ?0.5 * 1 to +7.0 * 3 v operating temperature range * 2 HN58V65AI/hn58v66ai topr ?40 to +85 c hn58v65a-sr/hn58v66a-sr topr ?20 to +85 c storage temperature range tstg ?55 to +125 c notes: 1. vin min : ?3.0 v for pulse width 50 ns. 2. including electrical characteristics and data retention. 3. should not exceed v cc + 1 v.
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 6 of 26 recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 2.7 ? 5.5 v v ss 0 0 0 v input voltage v il ?0.3 * 1 ? 0.6 * 5 v v ih 2.4 * 2 ? v cc + 0.3 * 3 v v h * 4 v cc ? 0.5 ? v cc + 1.0 v operating temperature topr HN58V65AI/hn58v66ai ?40 ? +85 c hn58v65a-sr/hn58v66a-sr ?20 ? +85 c notes: 1. v il min: ?1.0 v for pulse width 50 ns. 2. v ih = 3.0 v for v cc = 3.6 to 5.5 v. 3. v ih max: v cc + 1.0 v for pulse width 50 ns. 4. this function is supported by only the hn58v66a series. 5. v il = 0.8 v for v cc = 3.6 v to 5.5 v dc characteristics (ta = ? 40 to +85 c, v cc = 2.7 to 5.5 v: hn58v66ai/hn58v66ai, ta = ? 20 to +85 c, v cc = 2.7 to 5.5 v: hn58v66a-sr/hn58v66a-sr) parameter symbol min typ max unit test conditions input leakage current i li ? ? 2 * 1 a v cc = 5.5 v, vin = 5.5 v output leakage current i lo ? ? 2 a v cc = 5.5 v, vout = 5.5/0.4 v standby v cc current i cc1 ? 1 to 2 5 a ce = v cc i cc2 ? ? 1 ma ce = v ih operating v cc current i cc3 ? ? 6 ma iout = 0 ma, duty = 100%, cycle = 1 s at v cc = 3.6 v ? ? 10 ma iout = 0 ma, duty = 100%, cycle = 1 s at v cc = 5.5 v ? ? 15 ma iout = 0 ma, duty = 100%, cycle = 100 ns at v cc = 3.6 v ? ? 25 ma iout = 0 ma, duty = 100%, cycle = 70 ns at v cc = 5.5 v output low voltage v ol ? ? 0.4 v i ol = 2.1 ma output high voltage v oh v cc 0.8 ? ? v i oh = ? 400 a note: 1. i li on res : 100 a max (only the hn58v66a series)
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 7 of 26 capacitance (ta = +25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance cin * 1 ? ? 6 pf vin = 0 v output capacitance cout * 1 ? ? 12 pf vout = 0 v note: 1. this parameter is sampled and not 100% tested. ac characteristics (ta = ? 40 to +85 c, v cc = 2.7 to 5.5 v: HN58V65AI/hn58v66ai, ta = ? 20 to +85 c, v cc = 2.7 to 5.5 v: hn58v65a-sr/hn58v66a-sr) test conditions ? input pulse levels : 0.4 v to 2.4 v (v cc = 2.7 to 3.6 v), 0.4 v to 3.0 v (v cc = 3.6 to 5.5 v) 0 v to v cc ( res pin* 2 ) ? input rise and fall time : 5 ns ? input timing reference levels : 0.8, 1.8 v ? output load : 1ttl gate +100 pf ? output reference levels : 1.5 v, 1.5 v read cycle 1 (2.7 v cc < 4.5 v) HN58V65AI/hn58v66ai hn58v65a-sr/hn58v66a-sr -10 parameter symbol min max unit test conditions address to output delay t acc ? 100 ns ce = oe = v il , we = v ih ce to output delay t ce ? 100 ns oe = v il , we = v ih oe to output delay t oe 10 50 ns ce = v il , we = v ih address to output hold t oh 0 ? ns ce = oe = v il , we = v ih oe ( ce ) high to output float * 1 t df 0 40 ns ce = v il , we = v ih res low to output float * 1, 2 t dfr 0 350 ns ce = oe = v il , we = v ih res to output delay * 2 t rr 0 450 ns ce = oe = v il , we = v ih
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 8 of 26 write cycle 1 (2.7 v cc < 4.5 v) parameter symbol min * 3 typ max unit test conditions address setup time t as 0 ? ? ns address hold time t ah 50 ? ? ns ce to write setup time ( we controlled) t cs 0 ? ? ns ce hold time ( we controlled) t ch 0 ? ? ns we to write setup time ( ce controlled) t ws 0 ? ? ns we hold time ( ce controlled) t wh 0 ? ? ns oe to write setup time t oes 0 ? ? ns oe hold time t oeh 0 ? ? ns data setup time t ds 50 ? ? ns data hold time t dh 0 ? ? ns we pulse width ( we controlled) t wp 200 ? ? ns ce pulse width ( ce controlled) t cw 200 ? ? ns data latch time t dl 100 ? ? ns byte load cycle t blc 0.3 ? 30 s byte load window t bl 100 ? ? s write cycle time t wc ? ? 10 * 4 ms time to device busy t db 120 ? ? ns write start time t dw 0 * 5 ? ? ns reset protect time * 2 t rp 100 ? ? s reset high time * 2, 6 t res 1 ? ? s notes: 1. t df and t dfr are defined as the time at which the outpu ts achieve the open circuit conditions and are no longer driven. 2. this function is supported by only the hn58v66a series. 3. use this device in longer cycle than this value. 4. t wc must be longer than this value unless polling techniques or rdy/ busy are used. this device automatically completes the internal write operation within this value. 5. next read or write operat ion can be initiated after t dw if polling techniques or rdy/ busy are used. 6. this parameter is sampled and not 100% tested. 7. a6 through a12 are page addresses and these addresses are latched at the first falling edge of we . 8. a6 through a12 are page addresses and these addresses are latched at the first falling edge of ce . 9. see ac read characteristics.
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 9 of 26 read cycle 2 (4.5 v cc 5.5 v) HN58V65AI/hn58v66ai hn58v65a-sr/hn58v66a-sr -10 parameter symbol min max unit test conditions address to output delay t acc ? 70 ns ce = oe = v il , we = v ih ce to output delay t ce ? 70 ns oe = v il , we = v ih oe to output delay t oe 10 40 ns ce = v il , we = v ih address to output hold t oh 0 ? ns ce = oe = v il , we = v ih oe ( ce ) high to output float * 1 t df 0 30 ns ce = v il , we = v ih res low to output float * 1, 2 t dfr 0 350 ns ce = oe = v il , we = v ih res to output delay * 2 t rr 0 450 ns ce = oe = v il , we = v ih
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 10 of 26 write cycle 2 (4.5 v cc 5.5 v) parameter symbol min * 3 typ max unit test conditions address setup time t as 0 ? ? ns address hold time t ah 50 ? ? ns ce to write setup time ( we controlled) t cs 0 ? ? ns ce hold time ( we controlled) t ch 0 ? ? ns we to write setup time ( ce controlled) t ws 0 ? ? ns we hold time ( ce controlled) t wh 0 ? ? ns oe to write setup time t oes 0 ? ? ns oe hold time t oeh 0 ? ? ns data setup time t ds 50 ? ? ns data hold time t dh 0 ? ? ns we pulse width ( we controlled) t wp 100 ? ? ns ce pulse width ( ce controlled) t cw 100 ? ? ns data latch time t dl 50 ? ? ns byte load cycle t blc 0.2 ? 30 s byte load window t bl 100 ? ? s write cycle time t wc ? ? 10 * 4 ms time to device busy t db 120 ? ? ns write start time t dw 0 * 5 ? ? ns reset protect time * 2 t rp 100 ? ? s reset high time * 2, 6 t res 1 ? ? s notes: 1. t df and t dfr are defined as the time at which the outpu ts achieve the open circuit conditions and are no longer driven. 2. this function is suppor ted by only the hn58v66a. 3. use this device in longer cycle than this value. 4. t wc must be longer than this value unless polling techniques or rdy/ busy are used. this device automatically completes the internal write operation within this value. 5. next read or write operat ion can be initiated after t dw if polling techniques or rdy/ busy are used. 6. this parameter is sampled and not 100% tested. 7. a6 through a12 are page address and these addr esses are latched at the first falling edge of we . 8. a6 through a12 are page address and these addr esses are latched at the first falling edge of ce . 9. see ac read characteristics.
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 11 of 26 timing waveforms read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df t rr t dfr res * 2
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 12 of 26 byte write timing waveform(1) ( we controlled) address ce we oe din rdy/ busy t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh t db t rp res * 2 v cc t res high-z high-z t dw
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 13 of 26 byte write timing waveform(2) ( ce controlled) address ce we oe din rdy/ busy t wc t ah t ws t as t oeh t wh t oes t ds t dh t db t rp res * 2 v cc t cw t bl t dw t res high-z high-z
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 14 of 26 page write timing waveform(1) ( we controlled) address a0 to a12 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t ch t cs t wp t dl t blc t ds t dw high-z high-z * 7
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 15 of 26 page write timing waveform(2) ( ce controlled) address a0 to a12 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t wh t ws t cw t dl t blc t ds t dw high-z high-z * 8
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 16 of 26 data polling timing waveform t ce t oeh t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x * 9 * 9 an
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 17 of 26 toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/ o6 will charge from ?1? to ?0? (toggling) for each read. when the internal programming cycle is finish ed, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 beginning state is ?1?. 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh * 1 * 2 * 2 address * 3 * 3 * 4 din
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 18 of 26 software data protectio n timing waveform(1) (in protection mode) v ce we address data 1555 aa 0aaa 55 1555 a0 t blc t wc cc write address write data software data protectio n timing waveform(2) (in non-protection mode) v ce we address data t wc cc normal active mode 1555 aa 0aaa 55 1555 80 1555 aa 0aaa 55 1555 20
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 19 of 26 functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 s from the preceding falling edge of we or ce . when ce or we is kept high for 100 s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data polling data polling indicates the status that the eeprom is in a write cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs from i/o7 to indicate that the eeprom is performing a write operation. rdy/ busy signal rdy/ busy signal also allows status of th e eeprom to be determined. the rdy/ busy signal has high impedance except in write cycle and is lowered to v ol after the first write signal. at the end of a write cycle, the rdy/ busy signal changes state to high impedance. res signal (only the hn58v66a series) when res is low, the eeprom cannot be read or programmed. therefore, data can be protected by keeping res low when v cc is switched. res should be high during read and programming because it doesn?t provide a latch function. v program inhibit cc res program inhibit read inhibit read inhibit
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 20 of 26 we , ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce , and data is latched by the rising edge of we or ce . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data reten tion time is more than 10 years when a device is page-programmed less than 10 4 cycles. data protection to prevent this phenomenon, this device has a noise can cellation function that cuts noise if its width is 15 ns or less. 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. be careful not to allow noise of a width of more than 15 ns on the control pins. we ce oe v 0 v v 0 v 15 ns max ih ih
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 21 of 26 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom should be kept in unprogrammable state during v cc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * * 2.1 protection by ce , oe , we to realize the unprogrammable state, the input level of control pins must be held as shown in the table below. ce v cc oe v ss we v cc : don?t care. v cc : pull-up to v cc level. v ss : pull-down to v ss level.
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 22 of 26 2.2 protection by res (only the hn58v66a series) the unprogrammable state can be r ealized by that the cpu?s reset signal inputs directly to the eeprom?s res pin. res should be kept v ss level during v cc on/off. the eeprom breaks off programming operation when res becomes low, programming operation doesn?t finish correctly in case that res falls low during programming operation. res should be kept high for 10 ms after the last data input. v cc res we or ce 100 s min 10 ms min 1 s min program inhibit program inhibit
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 23 of 26 3. software data protection to prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. in software data protection mode, 3 bytes of data must be input before write data as follows. and these bytes can switch the non-protection mode to the protection mode. sdp is enabled if only the 3 byte code is input. data aa 55 a0 write data } address 1555 0aaa 1555 write address normal data input software data protection mode can be canceled by inputting the following 6 bytes. after that, this device turns to the non-protection mode and can write data normally. but when the data is input in the canceling cycle, the data cannot be written. data aa 55 80 aa 55 20 address 1555 0aaa 1555 1555 0aaa 1555 the software data protection is not enabled at the shipment. note: there are some differences be tween renesas technology?s and other company?s for enable/disable sequence of software data protection. if th ere are any questions, please contact with renesas technology?s sales offices.
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 24 of 26 package dimensions hn58v65api series hn58v66api series (dp-28, dp-28v) package code jedec jeita mass (reference value) dp-28, dp-28v ? conforms 4.6 g 0.51 min 2.54 min 0.25 + 0.11 ? 0.05 2.54 0.25 0.48 0.10 0 ? ? 15 ? 15.24 1.2 35.6 36.5 max 13.4 14.6 max 1 14 15 28 5.70 max 1.9 max unit: mm
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 25 of 26 package dimensions (cont) hn58v65afpi series hn58v66afpi series (fp-28d, fp-28dv) package code jedec jeita mass (reference value) fp-28d, fp-28dv conforms ? 0.7 g *dimension including the plating thickness base material dimension 0? ? 8? *0.17 0.05 1.0 0.2 0.20 0.10 2.50 max 8.4 18.3 18.8 max 1.12 max 28 15 1 14 11.8 0.3 1.7 0.20 0.15 m 1.27 *0.40 0.08 0.38 0.06 0.15 0.04 unit: mm
HN58V65AI/hn58v66ai/hn58v65 a-sr/hn58v66a-sr series rev.3.00, feb.02.2004, page 26 of 26 package dimensions (cont) hn58v65ati series hn58v66ati series hn58v65at-sr series hn58v66at-sr series (t fp-28db, tfp-28dbv) package code jedec jeita mass (reference value) tfp-28db, tfp-28dbv ? ? 0.23 g *dimension including the plating thickness base material dimension 0.10 m 0.55 8.00 *0.22 0.08 13.40 0.30 *0.17 0.05 0.13 1.20 max 11.80 0 ? ? 5 ? 28 1 14 15 8.20 max 0.10 +0.07 ?0.08 0.50 0.10 0.80 0.45 max 0.20 0.06 0.15 0.04 unit: mm
revision history HN58V65AI/hn58v66ai/hn 58v65a-sr/hn58v66a-sr series data sheet contents of modification rev. date page description 0.0 mar. 12, 1997 ? initial issue 1.0 aug. 29, 1997 ? 7 11 19 addition of hn58v65a-sr/hn58v66a-sr ac characteristics input pulse level: 0.4 v to v cc to 0 v to v cc timing waveform read timing waveform: correct error functional description data protection 3.: addition of description 2.0 oct. 31, 1997 6 dc characteristics i cc3 (max): 6/10/12/25 ma to 6/10/15/25 ma 3.00 feb. 02, 2004 2 24-26 ordering information addition of hn58v65api-10e, hn58v66api-10e, hn58v65afpi-10e, hn58v66afpi-10e, hn58v65ati-10e, hn58v66ati-10e, hn58v65at-10sre, hn58v66at-10sre package dimensions dp-28 to dp-28, dp-28v fp-28d to fp-28d, fp-28dv tfp-28db to tfp-28db, tfp-28dbv
? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas tech nology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices

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